The present application is also related to the following applications, all of which are filed simultaneously herewith, and which are hereby incorporated by reference as if fully set forth herein:
An application Ser. No. 10/029,077 entitled xe2x80x9cMEMORY CELL UTILIZING NEGATIVE DIFFERENTIAL RESISTANCE FIELD-EFFECT TRANSISTORSxe2x80x9d; and
An application Ser. No. 10/028,394 entitled xe2x80x9cDUAL MODE FET and LOGIC CIRCUIT HAVING NEGATIVE DIFFERENTIAL RESISTANCE MODExe2x80x9d;
An application Ser. No. 10/028,089 entitled xe2x80x9cCHARGE PUMP FOR NEGATIVE DIFFERENTIAL RESISTANCE TRANSISTORxe2x80x9d;
An application Ser. No. 10/028,085 entitled xe2x80x9cIMPROVED NEGATIVE DIFFERENTIAL RESISTANCE FIELD EFFECT TRANSISTOR (NDR-FET) and CIRCUITS USING THE SAMExe2x80x9d.
This invention provides a semiconductor device, having a variety of applications such as a bistable latch or a logic circuit, in which one or more insulated-gate field-effect transistor (IGFET) elements and one or more negative differential resistance (NDR) field-effect transistor elements are combined and formed on a common substrate. The present invention is applicable to a wide range of semiconductor integrated circuits, particularly for high-density memory and logic applications.
Devices that exhibit a negative differential resistance (NDR) characteristic, such that two stable voltage states exist for a given current level, have long been sought after in the history of semiconductor devices. A new type of CMOS compatible, NDR capable FET is described in the aforementioned applications to King et al. referenced above. The advantages of such device are well set out in such materials, and are not repeated here.
NDR devices and their applications are further discussed in a number of references, including the following that are hereby incorporated by reference and identified by bracketed numbers [ ] where appropriate below:
[1] P. Mazumder, S. Kulkarni, M. Bhattacharya, J. P. Sun and G. I. Haddad, xe2x80x9cDigital Circuit Applications of Resonant Tunneling Devices,xe2x80x9d Proceedings of the IEEE, Vol. 86, No. 4, pp. 664-686, 1998.
[2] W. Takao, U.S. Pat. No. 5,773,996, xe2x80x9cMultiple-valued logic circuitxe2x80x9d (issued Jun. 30, 1998)
[3] Y. Nakasha and Y. Watanabe, U.S. Pat. No. 5,390,145, xe2x80x9cResonance tunnel diode memoryxe2x80x9d (issued Feb. 14, 1995)
[4] J. P. A. Van Der Wagt, xe2x80x9cTunneling-Based SRAM,xe2x80x9d Proceedings of the IEEE, Vol. 87, No. 4, pp. 571-595, 1999.
[5] R. H. Mathews, J. P. Sage, T. C. L. G. Sollner, S. D. Calawa, C. -L. Chen, L. J. Mahoney, P. A. Maki and K. M Molvar, xe2x80x9cA New RTD-FET Logic Farnily,xe2x80x9d Proceedings of the IEEE, Vol. 87, No. 4, pp. 596-605, 1999.
[6] H. J. De Los Santos, U.S. Pat. No. 5,883,549, xe2x80x9cBipolar junction transistor (BJT)-resonant tunneling diode (RTD) oscillator circuit and method (issued Mar. 16, 1999)
[7] S. L. Rommel, T. E. Dillon, M. W. Dashiell, H. Feng, J. Kolodzey, P. R. Berger, P. E. Thompson, K. D. Hobart, R. Lake, A. C. Seabaugh, G. Klimeck and D. K. Blanks, xe2x80x9cRoom temperature operation of epitaxially grown Si/Si0.5Ge0.5/Si resonant interband tunneling diodes,xe2x80x9d Applied Physics Letters, Vol. 73, No. 15, pp. 2191-2193, 1998.
[8] S. J. Koester, K. Ismail, K. Y. Lee and J. O. Chu, xe2x80x9cNegative differential conductance in lateral double-barrier transistors fabricated in strained Si quantum wells,xe2x80x9d Applied Physics Letters, Vol. 70, No. 18, pp. 2422-2424, 1997.
[9] G. I. Haddad, U. K. Reddy, J. P. Sun and R. K. Mains, xe2x80x9cThe bound-state resonant tunneling transistor (BSRTT): Fabrication, d.c. I-V characteristics, and high-frequency properties,xe2x80x9d Superlattices and Microstructurer, Vol. 7, No. 4, p. 369, 1990.
[10] Kulkarni et. al., U.S. Pat. No. 5,903,170, xe2x80x9cDigital Logic Design Using Negative Differential Resistance Diodes and Field-Effect Transistors (issued May 11, 1999).
A wide range of circuit applications for NDR devices are proposed in the above references, including multiple-valued logic circuits [1,2], static memory (SRAM) cells [3,4], latches [5], and oscillators [6]. To date, technological obstacles have hindered the widespread use of NDR devices in conventional silicon-based integrated circuits (ICs). The most significant obstacle to large-scale commercialization has been the technological challenge of integrating high-performance NDR devices into a conventional IC fabrication process. The majority of NDR-based circuits require the use of transistors, so the monolithic integration of NDR devices with predominant complementary metal-oxide-semiconductor (CMOS) transistors is the ultimate goal for boosting circuit functionality and/or speed. Clearly, the development of a CMOS-compatible NDR device technology would constitute a break-through advancement in silicon-based IC technology. The integration of NDR devices with CMOS devices would provide a number of benefits including at least the following for logic and memory circuits:
1) reduced circuit complexity for implementing a given function;
2) lower-power operation; and
3) higher-speed operation.
Significant manufacturing cost savings could be achieved concomitantly, because more chips could be fabricated on a single silicon wafer without a significant increase in wafer-processing cost.
A tremendous amount of effort has been expended over the past several decades to research and develop silicon-based NDR devices in order to achieve compatibility with mainstream CMOS technology, because of the promise such devices hold for increasing IC performance and functionality. Efforts thus far have yielded NDR devices that require either prohibitively expensive process technology or extremely low operating temperatures which are impractical for high-volume applications. One such example in the prior art requires deposition of alternating layers of silicon and silicon-germanium alloy materials using molecular beam epitaxy (MBE) to achieve monolayer precision to fabricate the NDR device [7]. MBE is an expensive process which cannot be practically employed for high-volume production of semiconductor devices. Another example in the prior art requires the operation of a device at extremely low temperatures (1.4K) in order to achieve significant NDR characteristics [8]. This is impractical to implement for high-volume consumer electronics applications.
Three (or more) terminal devices are preferred as switching devices, because they allow for the conductivity between two terminals to be controlled by a voltage or current applied to a third terminal, an attractive feature for circuit design as it allows an extra degree of freedom and control in circuit designs. Three-terminal quantum devices which exhibit NDR characteristics such as the resonant tunneling transistor (RTT) [9] have been demonstrated; the performance of these devices has also been limited due to difficulties in fabrication, however. Some bipolar devices (such as SCRs) also can exhibit an NDR effect, but this is limited to embodiments where the effect is achieved with two different current levels. In other words, the current-vs.-voltage (I-V) curve of this type of device is not as useful because it does not provide two stable voltage states for a given current.
Accordingly, there exists a significant need for the monolithic integration of three-terminal NDR devices with conventional field-effect transistors by means of a single fabrication process flow.
A first object of the present invention is to provide a semiconductor device having a variety of applications such as bistable latch or logic circuits through the combination of one or more insulated-gate field-effect transistor (IGFET) elements and one or more negative differential resistance field-effect transistor (NDR-FET) elements.
A second object of the present invention is to provide a practical method of manufacturing a semiconductor device utilizing a single fabrication process flow, so that an IGFET and an NDR-FET can be formed on a common substrate.
For achieving the first object, the invention provides a semiconductor device comprising an IGFET including a gate and source/drain electrodes, and an NDR-FET including gate and source/drain electrodes, wherein the IGFET and NDR-FET elements are formed on a common substrate, and one of the gate or source/drain electrodes of the IGFET element is electrically connected with one of the source/drain electrodes of the NDR-FET. Thusly, various types of circuits having a variety of functions can be attained through the combination of an IGFET and an NDR-FET.
In one aspect of this invention, the NDR-FET can utilize silicon as the semiconductor material. Thus, the NDR-FET and the IGFET can be fabricated on a common silicon substrate and hence a semiconductor device incorporating one or more NDR elements and one or more conventional field-effect transistor elements can be practically realized.
In another aspect of this invention, the IGFET can be an n-channel enhancement-mode transistor, with the gate electrode and the drain electrode of the IGFET semiconductor element short-circuited and connected to a power-supply terminal, the source electrode of the IGFET electrically connected together with the drain electrode of the NDR-FET to a control terminal, the source of the NDR-FET connected to a grounded or negatively biased terminal, and the gate electrode of the NDR-FET biased at a constant voltage. Thus, among plural intersections between the current-vs.-voltage (I-V) characteristic of the NDR-FET and the I-V characteristic of the IGFET semiconductor element, an intersection at which the gradients (obtained as a change in current in accordance with a change of the control terminal voltage) of the characteristics have different signs (positive, negative, or zero) is a stable operating point of the semiconductor device. Therefore, the semiconductor device can function as a bistable memory cell.
In another aspect of this invention, the IGFET can be an n-channel enhancement-mode transistor, with the source electrode connected to a grounded or negatively-biased terminal, the gate electrode and the drain electrode of the IGFET semiconductor element short-circuited and electrically connected together with the source of the NDR-FET to a control terminal, the drain electrode of the NDR-FET connected to a power-supply terminal, and the gate electrode of the NDR-FET biased at a constant voltage. Thus, among plural intersections between the I-V characteristic of the NDR-FET and the I-V characteristic of the IGFET semiconductor element, an intersection at which the gradients (obtained as a change in current in accordance with a change of the control terminal voltage) of the characteristics have different signs (positive, negative, or zero) is a stable operating point of the semiconductor device. Therefore, the semiconductor device can function as a bistable memory cell.
In another aspect of this invention, the IGFET can be an n-channel depletion-mode transistor, with the gate electrode and the source electrode of the IGFET semiconductor element short-circuited and the drain electrode connected to a power-supply terminal, the source electrode of the IGFET electrically connected together with the drain electrode of the NDR-FET to a control terminal, the source of the NDR-FET connected to a grounded or negatively biased terminal, and the gate electrode of the NDR-FET biased at a constant voltage. Thus, among plural intersections between the I-V characteristic of the NDR-FET and the I-V characteristic of the IGFET semiconductor element, an intersection at which the gradients (obtained as a change in current in accordance with a change of the control terminal voltage) of the characteristics have different signs (positive, negative, or zero) is a stable operating point of the semiconductor device. Therefore, the semiconductor device can function as a bistable memory cell.
In another aspect of this invention, the IGFET can be an n-channel depletion-mode transistor, with the gate electrode and the source electrode of the IGFET semiconductor element short-circuited and connected to a grounded or negatively-biased terminal, the drain electrode of the IGFET electrically connected together with the source of the NDR-FET to a control terminal, the drain electrode of the NDR-FET connected to a power-supply terminal, and the gate electrode of the NDR-FET biased at a constant voltage. Thus, among plural intersections between the I-V characteristic of the NDR-FET and the I-V characteristic of the IGFET semiconductor element, an intersection at which the gradients (obtained as a change in current in accordance with a change of the control terminal voltage) of the characteristics have different signs (positive, negative, or zero) is a stable operating point of the semiconductor device. Therefore, the semiconductor device can function as a bistable memory cell.
In another aspect of this invention, the IGFET can be an n-channel enhancement-mode transistor, with one of the source/drain electrodes of the IGFET semiconductor element connected to the source electrode of a first NDR-FET and also to the drain electrode of a second NDR-FET, the gate electrode of the IGFET connected to a first control terminal, the other one of the source/drain electrodes of the IGFET connected to a second control terminal, the drain electrode of the first NDR-FET connected to a power-supply terminal, the source electrode of the second NDR-FET connected to a grounded or negatively-biased terminal, and the gate electrodes of the NDR-FETs each biased at a constant voltage. Thus, among plural intersections between the I-V characteristic of the first NDR-FET and the I-V characteristic of the second NDR-FET, an intersection at which the gradients (obtained as a change in current in accordance with a change of the control terminal voltage) of the characteristics have different signs (positive, negative, or zero) is a stable operating point of the semiconductor device. Therefore, the semiconductor device can function as a bistable memory cell, with access to the data storage node provided via the IGFET.
For achieving the second object, the invention provides a method of manufacturing a semiconductor device including an IGFET semiconductor element having a gate electrode, a gate insulating film and a channel region and source/drain regions of semiconductor, and a NDR-FET having a gate electrode, a gate insulating film and a channel region and source/drain regions of semiconductor, wherein the IGFET and NDR-FET elements are formed on a common substrate, and at least one of the gate or source/drain electrodes of the IGFET element is electrically connected to one of the source/drain electrodes of the NDR-FET.
The method comprises the following steps: simultaneously forming electrically isolated xe2x80x9cactivexe2x80x9d regions for the IGFET and NDR-FET elements in the surface of a semiconductor substrate; sequentially and separately adjusting the NDR-FET and IGFET channel dopant concentrations in the surface regions of the semiconductor substrate; forming the gate insulating films for the NDR-FET and IGFET elements by thermal oxidation and/or thin-film deposition; selectively forming charge traps in the gate insulating film or at the interface between the gate insulating film and the semiconductor channel of the NDR-FET element either by ion implantation and/or diffusion of an appropriate species or by depositing a charge-trapping layer either before or after part or all of the NDR-FET gate insulating film has been formed; forming contact holes in the source or drain region of the IGFET if needed; blanket depositing a gate-electrode material on the gate insulating films of the IGFET and the NDR-FET elements; simultaneously completing the fabrication of the IGFET and NDR-FET elements using conventional IC fabrication process steps to pattern the gate electrodes, dope the gate electrodes and form the source and drain electrodes, deposit passivation layer(s), and form interconnects.
In one aspect, the IGFET and NDR-FET may be fabricated side-by-side in the same active region, or xe2x80x9cwell.xe2x80x9d
In another aspect, the semiconductor substrate is monocrystalline silicon.
In another aspect, the semiconductor substrate is a silicon-on-insulator (monocrystaline silicon layer on top of an electrically insulating SiO2 layer on top of a silicon wafer) substrate.
In another aspect, the channel dopant concentration in the NDR-FET may be substantially different from the channel dopant concentration in the IGFET.
In another aspect, a portion or all of the gate insulating film for the NDR-FET may be formed before the gate insulating film for the IGFET is formed.
In another aspect, the semiconductor substrate may contain one or mote layers of silicon-germanium in either or both of the IGFET and NDR-FET active regions.
In another aspect, the thickness of the gate insulating film in the NDR-FET may be substantially different from the thickness of the gate insulating film in the IGFET.
In another aspect, formation of charge traps in the gate insulating film of the NDR-FET is facilitated by incorporating boron, which may be achieved by thermal oxidation of a boron-doped channel and/or thermal diffusion of boron from the channel into the gate insulating film.
In another aspect, charge traps are formed in the gate insulating film of the NDR-FET by depositing a layer of material, such as silicon or silicon-rich oxide, after a portion of the gate insulating film has been formed, and before the remaining portion of the gate insulating film is formed. The deposited layer may be continuous, in the form of a thin film, or it may be discontinuous, in the form of islands.
In another aspect, charge traps are formed in the gate insulating film of the NDR-FET by depositing a layer of material which contains a high density of charge traps, such as silicon-rich oxide, silicon oxynitride, silicon nitride, or high-permittivity dielectric, before the remaining portion of the gate insulating film is formed.
In another aspect, charge traps are formed in the gate insulating film of the NDR-FET by implantation of arsenic, phosphorus, fluorine, silicon, germanium, nitrogen, or metallic atoms.
In another aspect, a polycrystalline silicon (poly-Si) or polycrystalline silicon-germanium (poly-SiGe) film can be deposited as the gate-electrode material.
In another aspect, a metal or conductive metal-nitride or conductive metal-oxide or metal-silicide film can be deposited as the gate-electrode material.
In this manner, a semiconductor device comprising one or more IGFET elements and one or more NDR-FET elements can be manufactured on a common substrate utilizing a fabrication sequence consisting of conventional process steps. Accordingly, the manufacture of the semiconductor device can be eased and the manufacturing cost can be relatively low.